Battery mounted integrated circuit device

ABSTRACT

The present invention relates to a battery mounted integrated circuit device where an integrated circuit and a solid state battery are formed on the same substrate. In this battery mounted integrated circuit device, a first diffusion layer containing an N-type impurity is formed between a region of a semiconductor substrate where the solid state battery is mounted and a region of the semiconductor substrate where the integrated circuit is mounted, and a second diffusion layer containing an N-type impurity is formed below the region of the semiconductor substrate where the solid state battery is mounted, and overlaps with the first diffusion layer.

TECHNICAL FIELD

The present invention relates to a battery mounted integrated circuitdevice constituted by the coexistence of an integrated circuit and asolid state battery.

BACKGROUND ART

In recent years, with size reduction in electronic devices, an all-solidstate battery has been formed together with semiconductor devices on asemiconductor substrate. In such a semiconductor substrate, in somecases, ions which serve to charge/discharge a solid state battery, e.g.lithium ions, diffuse to the semiconductor substrate. When those ionshaving diffused in the semiconductor substrate reach semiconductordevices, there are possibilities that the characteristics of thesemiconductor devices deteriorate or the semiconductor devicesimproperly operate.

Regarding such a battery mounted integrated circuit device as describedabove where semiconductor devices and a solid state battery are formedon the same semiconductor substrate, as a method for reducing aninfluence on the semiconductor substrate exerted by ions serving tocharge/discharge the solid state battery, it has been proposed that adiffusion layer be formed by doping an N-type impurity into thesemiconductor substrate directly under the solid state battery, and thisdiffusion layer be applied with a potential not lower than a potentialof a positive electrode of the solid state battery (Japanese Laid-Openpatent Publication No. 2003-133420).

The diffusion layer applied with a potential not lower than thepotential of the positive electrode of the solid state battery canprevent positive ions serving to charge/discharge the solid statebattery, e.g. lithium ions, from diffusing into the semiconductorsubstrate. This can prevent the ions serving to charge/discharge thesolid state battery from causing deterioration in characteristics of thesemiconductor devices and improper operations of the semiconductordevices.

However, in the configuration as described above, a contact resistancebetween the diffusion layer and an electrode for applying a potentialincreases when a potential higher than the potential of the positiveelectrode of the solid state battery is applied. In order to reduce thiscontact resistance, it is necessary to increase the concentration of theN-type impurity in the diffusion layer directly under the solid statebattery.

When the area of the solid state battery occupied on the substrate issmall, a region for the diffusion layer to be formed can be made small.This can decrease an amount of the N-type impurity required to increasethe concentration of the N-type impurity in the diffusion layer.However, when the area of the solid state battery occupied on thesubstrate is large, the region for the diffusion layer to be formedincreases. This leads to an increase in amount of the N-type impurityrequired for increasing the concentration of the N-type impurity in thediffusion layer. Further, with the increase in amount of the N-typeimpurity required, the time required for the formation of the diffusionlayer also increases. As thus described, a problem of lowering theproduction efficiency may arise as the solid state battery formed on thesemiconductor substrate becomes larger.

Accordingly, an object of the present invention is to provide a batterymounted integrated circuit device capable of effectively preventingdeterioration in characteristics of semiconductor devices and improperoperation of the semiconductor devices, without using a large amount ofN-type impurity.

DISCLOSURE OF INVENTION

The present invention relates to a battery mounted integrated circuitdevice, comprising: (1) a semiconductor substrate; (2) a solid statebattery mounted on the semiconductor substrate; (3) an integratedcircuit mounted on the semiconductor substrate; (4) a first diffusionlayer, containing an N-type impurity, formed between a region of thesemiconductor substrate where the solid state battery is mounted and aregion of the semiconductor substrate where the integrated circuit ismounted; and (5) a second diffusion layer, containing an N-typeimpurity, formed below the region of the semiconductor substrate wherethe solid state battery is mounted, and overlapping with the firstdiffusion layer. The solid state battery comprises a positive electrode,a negative electrode, and a solid electrolyte disposed between thepositive electrode and the negative electrode, and the concentration ofthe N-type impurity in the first diffusion layer is higher than theconcentration of the N-type impurity in the second diffusion layer.

It is preferable in the battery mounted integrated circuit device thatthe concentration of the N-type impurity in the first diffusion layer benot less than 1×10¹⁹ atoms/cm³.

It is further preferable in the battery mounted integrated circuitdevice that the ratio of the concentration of the N-type impurity in thefirst diffusion layer to the concentration of the N-type impurity in thesecond diffusion layer be not more than 1×10⁵.

It is further preferable in the battery mounted integrated circuitdevice that the first diffusion layer and the second diffusion layerhave a positive potential.

It is preferable that the positive potential be not less than apotential of the positive electrode with respect to the negativeelectrode.

It is preferable in the battery mounted integrated circuit device thatthe first diffusion layer surrounds the region where the solid statebattery be mounted.

It is preferable that the battery mounted integrated circuit devicefurther comprise a wiring layer for connecting the first diffusion layerwith the outside.

It is preferable that the battery mounted integrated circuit devicefurther comprise a potential controlling part for controlling apotential to be applied to the first diffusion layer and the seconddiffusion layer.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a vertical sectional view showing a main part of a batterymounted integrated circuit device in accordance with one embodiment ofthe present invention.

FIG. 2 is a plan view of a battery mounted integrated circuit device inaccordance with another embodiment of the present invention.

FIG. 3 is a sectional view cut along the line III-III of FIG. 2.

FIG. 4A, FIG. 4B, FIG. 4C and FIG. 4D are vertical sectional viewsshowing the process for producing the battery mounted integrated circuitdevice in FIG. 1.

BEST MODE FOR CARRYING OUT THE INVENTION

In the following, a battery mounted integrated circuit device of thepresent invention is described with reference to drawings.

EMBODIMENT 1

FIG. 1 shows a battery mounted integrated circuit device in accordancewith one embodiment of the present invention.

The battery mounted integrated circuit device 10 in FIG. 1 comprises asemiconductor substrate 11, and a solid state battery 12 and anintegrated circuit (not shown) which are mounted on the semiconductorsubstrate 11. The battery mounted integrated circuit device 10 furthercomprises a first diffusion layer 13 containing an N-type impurity,formed between a region 18 of the semiconductor substrate 11 where thesolid state battery 12 is mounted and a region 19 of the semiconductorsubstrate 11 where the integrated circuit is mounted, and a seconddiffusion layer 14 containing an N-type impurity formed below the region18 of the semiconductor substrate 11 where the solid state battery 12 ismounted. Herein, an insulating layer 15 is formed on the surface of thesemiconductor substrate 11. Further, a wiring layer 16 formed on thesemiconductor substrate 11 is connected to the first diffusion layer 13.The first diffusion layer 13 and the second diffusion layer 14 areoverlapped. The first diffusion layer 13 may be formed in the seconddiffusion layer 14.

The solid state battery 12 comprises a negative electrode currentcollector film 121, a negative electrode film 122, a solid electrolytefilm 123, a positive electrode film 124 and a positive electrode currentcollector film 125, which are successively layered on the semiconductorsubstrate 11. The positions of the positive electrode and the negativeelectrode may be reversed.

In the present embodiment, the solid state battery 12 is protected by asurface protective layer 17.

Various kinds of materials can be used for the semiconductor substrate11. For example, a silicon substrate, a sapphire substrate, as well assubstrates comprising silicon nitride, alumina, quartz and the like, canbe cited.

As the insulating layer 15 on the surface of the semiconductor substrate11, those capable of insulating the semiconductor substrate 11 and thenegative electrode current collector film 121 can be used. Examples ofthe insulating layer 15 include a material comprising a silicon oxidefilm and materials comprising silicon nitride, alumina, quartz, andresins such as polyimide.

In the case of forming a silicon oxide film as the insulating layer on asemiconductor substrate, for example, a plasma CVD method is employed toform an insulating layer, comprising a silicon oxide film, on asemiconductor substrate. The silicon oxide film can secure theinsulating property thereof when having a thickness of about 500 Å.

As the N-type impurity, a pentavalent element such as phosphorous orarsenic can be used.

As the negative electrode current collector film 121, a film comprisinga negative electrode current collector material capable of forming athin film can be employed. Examples of the negative electrode currentcollector material include copper and nickel.

As the negative electrode film 122, a film comprising a negativeelectrode material capable of forming a thin film can be used. Examplesof the negative electrode include graphite and lithium.

As the positive electrode 124, a film comprising a positive electrodematerial capable of forming a thin film can be used. Examples of thepositive electrode material include LiCoO₂ and LiMn₂O₄.

As the positive electrode current collector film 125, a film comprisinga positive electrode current collector material capable of forming athin film can be employed. Examples of the positive electrode currentcollector material include aluminum and nickel.

As the solid electrolyte film 123, a lithium-ion conductive solidelectrolyte, a silver-ion conductive solid electrolyte, a copper-ionconductive solid electrolyte, and the like can be used according to theelectrode materials.

As the lithium-ion conductive solid electrolyte used can be Li₂S—SiS₂,Li₃PO₄—Li₂S—SiS₂, LiI-Li₂S—SiS₂, LiI, LiI-Al₂O₃, Li₃N, Li₃N—LiI-LiOH,Li₂O—SiO₂, Li₂O—B₂O₃, LiI-Li₂S—P₂O₅, LiI-Li₂S—B₂S₃,Li_(3.6)Si_(0.6)P_(0.4)O₄, LiI-Li₃PO₄—P₂S₅, and the like. Further, anorganic dry polymer, such as polyethylene oxide, can be used as thelithium-ion conductive solid electrolyte.

When the lithium-ion conductive solid electrolyte is used, compoundscommonly used for lithium batteries such as Li_(x)CoO₂, Li_(x)NiO₂,Li_(x)Mn₂O₄, Li_(x)TiS₂, Li_(x)MoS₂, Li_(x)MoO₂, Li_(x)V₂O₅,Li_(x)V₆O₁₃, metallic lithium and Li_(3/4)Ti_(5/3)O₄, can be used as theelectrode material by combining those so as to obtain a desired batteryvoltage. It is to be noted that in the above compounds, 0<x<2 should besatisfied.

As the copper-ion conductive solid electrolyte used can beRbCu₄I_(1.5)Cl_(3.5), CuI-Cu₂O—MoO₃, Rb₄Cu₁₆I₇Cl₁₃ and the like.

When a copper-ion conductive material is used as the solid electrolyte,metallic Cu, Cu₂S, Cu_(x)TiS₂, Cu₂Mo₆S_(7.8) and the like can be used asthe electrode material.

As the silver-ion conductive solid electrolyte used can be α-AgI,Ag₆I₄WO₄, C₆H₅NHAg₅I₆, AgI-Ag₂O—MoO₃, AgI-Ag₂O—B₂O₃, AgI-Ag₂O—V₂O₅ andthe like.

When the silver-ion conductive solid electrolyte is used, metallic Ag,Ag_(0.7)V₂O₅, Ag_(x)TiS₂ and the like can be used as the electrodematerial.

The negative electrode current collector film, the positive electrodecurrent collector film, the negative electrode film, the positiveelectrode film and the solid electrolyte film can be produced by thevacuum deposition method, the sputtering method and the like.

As the wiring layer 16, a layer comprising a conductive material can beused. Aluminum and the like can be cited as this conductive material

Next, the first diffusion layer 13 and the second diffusion layer 14 aredescribed.

As thus described, the first diffusion layer 13 is disposed between theregion of the semiconductor substrate where the solid state battery ismounted and the region of the semiconductor substrate where theintegrated circuit is mounted, and the second diffusion layer 14 isdisposed below the region where the solid state battery is mounted.Further, the first diffusion layer 13 and the second diffusion layer 14are overlapped. In such a configuration, when a positive potential isapplied to the first diffusion layer 13 through the wiring layer, apotential in the second diffusion layer below the region of thesemiconductor substrate where the solid state battery is mounted alsobecomes positive.

In the case of a lithium solid state battery, for example, lithium ionsas cations serve to charge/discharge the solid state battery. Sincepotentials of the first diffusion layer 13 and the second diffusionlayer 14 are positive, the lithium ions as cations are electricallyrepulsive to the first diffusion layer 13 and the second diffusion layer14. This enables prevention of the lithium ions from diffusing beyondthe first diffusion layer 13 and the second diffusion layer 14 into theentire semiconductor substrate. Therefore, even when a pinhole, a crackor the like has been created in the current collector film 121 or theinsulating layer 15, it is possible to prevent cations serving tocharge/discharge a solid state battery, such as lithium ions, fromdiffusing from the solid state battery to the circuit-formed region whenthe solid state battery is charged/discharged.

Further, in the present invention, the concentration of the N-typeimpurity in the first diffusion layer is higher than the concentrationof the N-type impurity in the second diffusion layer. This can reducethe contact resistance between the wiring layer 16 and the firstdiffusion layer 13 connected to the wiring layer 16. It is therebypossible, unlike the conventional configuration, to apply a positivepotential to the second diffusion layer 14 through the first diffusionlayer.

As thus described, the disposition of the first diffusion layer 13having a higher concentration of the N-type impurity eliminates thenecessity to increase the concentration of the N-type impurity in thesecond diffusion layer 14, and the amount of the N-type impurity to beused can thereby be reduced.

Moreover, the concentration of the N-type impurity in the firstdiffusion layer is preferably from 1×10¹⁹ atoms/cm³ to 1×10²³ atoms/cm³,and further preferably from 1×10²⁰ atoms/cm³ to 1×10²² atoms/cm³. Whenthe concentration of the N-type impurity in the first diffusion layer isnot less than 1×10¹⁹ atoms/cm³, it is possible to suppress fluctuationof the potential in the first diffusion layer.

On the other hand, when the concentration of the N-type impurity in thefirst diffusion layer is more than 1×10²³ atoms/cm³, it becomesnecessary to further increase the concentration of the N-type impurityin the second diffusion layer, which undesirably causes an increase inamount of the N-type impurity to be used.

Furthermore, the ratio of the concentration of the N-type impurity inthe first diffusion layer to the concentration of the N-type impurity inthe second diffusion layer is preferably from 1×10¹ to 1×10⁵, and morepreferably from 1×10² to 1×10³.

When the ratio of the concentration of the N-type impurity in the firstdiffusion layer to the concentration of the N-type impurity in thesecond diffusion layer is not less than 1×10¹, in the case where a solidstate battery comprising a unit cell is mounted, diffusion of thecations in the semiconductor substrate can be prevented with certainty,thereby allowing the battery mounted integrated circuit device to havehigh reliability.

On the other hand, when the above concentration ratio exceeds 1×10⁵, thebreakdown voltage of the first diffusion layer 13 or the seconddiffusion layer 14 decreases, and a desired voltage cannot thus beapplied.

The N-type impurity contained in the first diffusion layer and theN-type impurity contained in the second diffusion layer may be the samekind of elements, or different kinds of elements. Further, plural kindsof pentavalent elements may be mixed and then used as the N-typeimpurity.

The sizes as well as depths of the first diffusion layer 13 and thesecond diffusion layer 14 are decided as appropriate according to thesize of a semiconductor substrate to be used, the size of a solid statebattery to be mounted on the semiconductor substrate, and the like.

It is preferable that the positive potential to be applied to the firstdiffusion layer 13 and the second diffusion layer 14 be a potential notlower than the potential in the positive electrode with reference to thenegative electrode. This is because the ions serving to charge/dischargethe secondary battery, for example, alkali metal ions such as Li⁺ ions,out from the positive electrode, tend to be attracted to an area, suchas the negative electrode, where a potential is lower than in thepositive electrode.

Further, the positive potential not lower than the potential in thepositive electrode with reference to the negative electrode may beapplied only when the solid state battery is charged/discharged, or maybe applied on a steady basis. For example, the positive potential can beapplied to the breakdown voltage of the first diffusion layer 13 or thesecond diffusion layer 14, if the characteristics of the battery and thesemiconductor circuit would not be affected.

As a power source for the application of the positive potential, theabove solid state battery may be used, or a different power source maybe used.

Further, in the present invention, in place of the solid state battery12 comprising a unit cell, a battery obtained by connecting in series orparallel solid state batteries each comprising a plurality of unit cellsstacked or solid state batteries each comprising a unit cell, may beused. In this case, since a voltage of the solid state battery variesdepending on the number of unit cells stacked, or the like, it ispreferable that positive potential higher than the voltage of this solidstate battery be applied to the first diffusion layer 13 and the seconddiffusion layer 14.

Controlling the positive potential in the above described manner may beconducted by a potential controlling part. In this case, the magnitudeof the positive potential can be controlled by previously setting to thepotential controlling part the magnitude of the positive potential to beapplied to the diffusion layers 13 and 14. The potential in the positiveelectrode with reference to the negative electrode may be detected andthe positive potential not lower than the detected potential may beapplied. Herein, the potential controlling part may comprise a powersource section for applying the positive potential.

Moreover, the positive potential may be applied to the diffusion layers13 and 14 on a steady basis by the potential controlling part; thepositive potential may be applied to the diffusion layers 13 and 14 onlywhen the solid state battery is charged/discharged. Further, thispotential controlling part may be disposed either in or outside of thebattery mounted integrated circuit device.

Next, one example of methods for producing the first diffusion layer 13and the second diffusion layer 14 is shown.

The first-diffusion layer 13 including the N-type impurity can be formedfor example by ion implantation of the N-type impurity between theintegrated circuit mounted region and the solid state battery mountedregion when an integrated circuit comprising semiconductor devices isformed on a semiconductor substrate. For example, the first diffusionlayer having a width of 0.5 mm and a thickness of 0.2 μm can be formedunder the implantation conditions of an accelerating voltage of theN-type impurity of 40 keV, and a doze amount thereof of 4.0×10¹⁵/cm².

The second diffusion layer 14 including the N-type impurity can beformed, for example, as follows. Before the first diffusion layer isformed, ion implantation of the N-type impurity is performed in thesolid state battery mounted region. The implantation conditions are, forexample, an accelerating voltage of the N-type impurity of 100 keV, anda doze amount thereof of 5.0×10¹⁵/cm². Subsequently, heat treatment isconducted at 1000° C. for 60 minutes. Accordingly, the second diffusionlayer 14 having a width of 10 mm and a thickness of 3 μm can be formed.

As thus described, because the second diffusion layer 14 requires theheat treatment, it is preferably formed before the formation of thefirst diffusion layer.

Moreover, the concentration of the N-type impurity in the firstdiffusion layer 13 and the second diffusion layer 14 can be controlledas appropriate by adjusting the accelerating voltage and the doze amountof the N-type impurity when the first diffusion layer 13 and the seconddiffusion layer 14 are formed.

EMBODIMENT 2

A description is given to a battery mounted integrated circuit device,where the first diffusion layer is formed so as to surround the regionwhere the solid state battery is mounted, with reference to FIGS. 2 and3.

In the battery mounted integrated circuit device 20 in FIG. 2, a solidstate battery 22 and an integrated circuit (not shown) are mounted on asemiconductor substrate 21. As shown in FIG. 3, a first diffusion layer23 containing an N-type impurity is formed between a region 28 of thesemiconductor substrate 21 where the solid state battery 22 is mountedand a region 29 of the semiconductor substrate 21 where the integratedcircuit is mounted. Further, a second diffusion layer 24 containing theN-type impurity is formed below the region 28 of the semiconductorsubstrate 21 where the solid state battery 22 is mentioned. Herein, asin the case of Embodiment 1 above, the insulating layer 25 is formed onthe surface of the semiconductor substrate 21. Further, the wiring layer26 formed on the semiconductor substrate 21 is connected to the firstdiffusion layer 23. The first diffusion layer 23 and the seconddiffusion layer 24 are overlapped. The first diffusion layer 23 may beformed in the second diffusion layer 24.

Also in the present embodiment, the concentration of the N-type impurityin the first diffusion layer 23 is higher than the concentration of theN-type impurity in the second diffusion layer 24. Further, theconcentration of the N-type impurity in the first diffusion layer 23,and the ratio of the concentration of the N-type impurity in the firstdiffusion layer 23 to the concentration of the N-type impurity in thesecond diffusion layer 24 are the same as in the case of Embodiment 1above.

The solid state battery 22 comprises a negative electrode currentcollector film 221, a negative electrode film 222, a solid electrolytefilm 223, a positive electrode film 224 and a positive electrode currentcollector film 225 which are successively stacked on the semiconductorsubstrate 21. The positions of the positive electrode and the negativeelectrode may be reversed.

For the semiconductor substrate 21, the solid state battery 22, theN-type impurity and the like, the same materials as in Embodiment 1above can be used.

In the present embodiment, the first diffusion layer 23 is formed so asto surround the region where the solid state battery is mounted. Withthis configuration, not only a potential directly under the solid statebattery, but a potential at the periphery of the solid state battery canbe made positive by applying a potential not lower than the potential ofthe positive electrode with reference to the negative electrode. It isthereby possible to control movement of ions serving to charge/dischargethe solid state battery from the region surrounded by the firstdiffusion layer 23, and also to freely dispose an integrated circuit onthe periphery of the region.

Further, the positive potential not lower than the potential of thepositive electrode with reference to the negative electrode may beapplied only when the solid state battery is charged/discharged, or maybe applied on a steady basis. Moreover, the positive potential can becontrolled by means of the potential controlling part as in Embodiment 1above.

The sizes as well as the depths of the first diffusion layer 13 and thesecond diffusion layer 14 are decided as appropriate according to thesize of a semiconductor substrate to be used, the size of a solid statebattery to be mounted on the semiconductor substrate, and the like, asin Embodiment 1 above.

In the following, the present invention is described based on examples.

EXAMPLE 1

The battery mounted integrated circuit device as shown in FIG. 1 wasproduced by the processes shown in FIGS. 4A to 4D. FIGS. 4A to 4D mainlyshow production methods of the first diffusion layer, the seconddiffusion layer and the solid state battery.

On a silicon substrate 31 shown in FIG. 4A (1), a silicon oxide film 32having a thickness of 1500 Å was formed by the plasma CVD method.Herein, the silicon substrate 31 was P-type and had a diameter of 4inches, a thickness of 525 μm, and a specific resistance of 10 to 15Ω·cm. In the plasma CVD method, SiH₄ and N₂O were used as reactivegases, and these reactive gases were irradiated with a low frequency of50 kHz frequency at an output of 4 kW to generate plasma. Further, thegrowth temperature of the silicon oxide film 32 was 380° C.

A photosensitive resist was applied on the silicon oxide film 32. Inthis application, a spin coater at a rotation speed of 2000 rpm was usedand the applied photosensitive resist had a thickness of 3000 Å. Afterthe application, heat treatment was conducted at 100° C. for 15 minutes,to form a resist film 33 (FIG. 4A(2)).

Next, as shown in FIG. 4A(3), the resist film 33 was irradiated with alight with short wavelength (wavelength: 436 nm) using a stepper.Herein, a quartz mask 34 having been patterned to have an opening 35 wasused.

Subsequently, the resist film 33 was patterned by being immersed in adeveloper comprising organic alkali (tetramethylammonium hydroxide).

Next, a portion of a silicon oxide film 32, which was uncoated with theresist film 33, was etched by RIE (Reactive Ion Etching) dry etching,and only a silicon oxide film 36 coated with the resist film was left.

Herein, in the dry etching, a high frequency of 13.56 MHz, and CHF₃ asan etching gas were used. Further, a mark for the alignment of masks wassimultaneously formed. In the subsequent resist exposure process, thealignment of masks was done by using this mark. This preventedmisalignment of films formed and patterned in the subsequent processes.

The resist film left on the silicon oxide film 36 was immersed in aresist stripper to be removed. Next, phosphorus was ion-implanted, bymeans of an ion implanter, into a portion of the silicon substrate 31,which was uncoated with the silicon oxide film 36 (FIG. 4A(4)). Herein,an accelerating voltage of phosphorus was 100 KeV and a dose amountthereof was 5×10¹²/cm².

Thereafter, heat treatment was conducted in a furnace at 1000° C. for 1hour to form a second diffusion layer 37 containing the N-type impurity(FIG. 4B(5)). Herein, the formed second diffusion layer 37 had a depthof 3 μm and an area of 100 mm² (10 mm (length)×10 mm (width)). Further,the concentration of the N-type impurity contained in the seconddiffusion layer 37 was measured, using SIMS (Secondary Ion MassSpectrometry), to be 1×10¹⁶/cm³.

Next, a silicon oxide film 38 having a thickness of 1500 Å was formed onthe silicon oxide film 36 and the second diffusion layer 37, using theplasma CVD method (FIG. 4B(6)). Herein, in the plasma CVD method, SiH₄and N₂O were used as reactive gases, and these reactive gases wereirradiated with a low frequency of 50 kHz frequency at an output of 4 kWto generate plasma. Further, the growth temperature of the silicon oxidefilm 38 was 380%.

A photosensitive resist was applied on the silicon oxide film 38 so asto have a thickness of 3000 Å. In this application, a spin coater at arotation speed of 2000 rpm was used. Subsequently, heat treatment wasconducted at 100% for 15 minutes, to form a resist film 39 (FIG. 4B(7)).

Using a quartz mask 40 having been patterned to have an opening 41, theresist film 39 was irradiated with a light with short wavelength (FIG.4B(8)). Herein, a stepper was used for the irradiation of the light withshort wavelength. Thereafter, the resist film 39 was patterned by beingimmersed in a developer comprising organic alkali (tetramethylammoniumhydroxide). Thereby, the resist film 39 over a portion for forming thefirst diffusion layer was removed.

Next, the silicon oxide film 38 on the portion with the resist film 39removed was etched by RIE dry etching to be removed. By this removal,the silicon substrate in the portion for forming the first diffusionlayer was exposed. Thereafter, the remaining resist film 39 was immersedin a resist stripper to be removed.

Herein, in the dry etching, a high frequency of 13.56 MHz and CHF₃ as anetching gas were used.

In the silicon-substrate-exposed portion formed in the above-describedmanner, arsenic as the N-type impurity was ion planted using an ionplanter. Herein, an accelerating voltage of arsenic was 40 KeV and adose amount thereof was 4×10¹⁵/cm² (FIG. 4C(9)).

In this manner, the first diffusion layer 42 containing the N-typeimpurity was formed (FIG. 4C(10)). Herein, the first diffusion layer 42had a depth of 0.2 μm and an area of 4.75 mm² (0.5 mm (length)×9.5 mm(width)). Further, the concentration of the N-type impurity (in thiscase, phosphorous and arsenic) contained in the first diffusion layer 42was measured, using SIMS, and as a result of the measurement, theimpurity concentration was 1×10²⁰/cm³. Accordingly, the ratio of theconcentration of the N-type impurity in the first diffusion layer to theconcentration of the N-type impurity in the second diffusion layer was1×10⁴/cm³.

Next, the silicon oxide films 36 and 38 were removed by being immersedin an aqueous solution of hydrofluoric acid (5 vol %) for 10 minutes.

The steps up to here were performed simultaneously with the formation ofthe integrated circuit (MOS transistor).

Next, on the silicon substrate 31 where the first diffusion layer andthe second diffusion layer were formed, a polyimide film 43 having athickness of 1 μm was formed using a spin coater at a rotation speed of1000 rpm (FIG. 4C(11)).

Thereafter, using the photolithography technique as described above, thepolyimide film 43 was patterned to have dimensions: 15 mm (length)×15 mm(width) (area: 225 mm²). In this manner, the portion of the siliconsubstrate where the first diffusion layer 42 was formed was exposed.

Next, a metallic aluminum film having a thickness of 1 μm and an area of81 mm² (9 mm (length)×9 mm (width)) was formed on the portion of thesilicon substrate where the first diffusion layer 42 was formed, and thepolyimide film 43, using a vacuum vapor deposition device with a chamberinternal pressure of 10 m Torr. This metallic aluminum film waspatterned using the above-described photolithography technique and RIEdry etching device, to form a positive electrode current collector film45 and a wiring layer 44 connected to the first diffusion layer 42 (FIG.4D(12)).

A film comprising LiCoO₂ was formed on the positive electrode currentcollector film 45 by RF magnetron sputtering method. Herein, aprescribed metallic mask (made of SUS304) was used so that the filmformed had a thickness of 5 μm and an area of 64 mm² (8 mm (length)×8 mm(width)). Further, in the sputtering, the output of the irradiation beamto a target was 200 W, a mixed gas of Ar and O₂ was used as a sputteringgas (Ar:O₂=3:1), the amount of the sputtering gas introduced was 20 SCCMand the internal pressure of the chamber was 20 m Torr.

Subsequently, the film comprising LiCoO₂ was annealed at 400% for 2hours to form a positive electrode film 46.

On the positive electrode film 46, a solid electrolyte film 47comprising Li₂S—SiS₂—Li₃PO₄ and having a thickness of 2 μm was formed.Subsequently, on the solid electrolyte film 47, a negative electrodefilm 48 comprising graphite and having a thickness of 5 μm was formed.In the formation of the solid electrolyte film 47 and the negativeelectrode film 48, a laser ablation method was used. In the laserablation method, the internal pressure of the chamber was 10⁻² Torr andthe temperature of the silicon substrate 31 was 800° C. As the laserused was a YAG laser having a wavelength of 266 nm and an energy densityof 2025 mJ/cm². The repetition frequency of the YAG laser was 10 Hz andthe number of shots thereof was 36000.

Using the above-described photolithography technique and RIE dryetching, the solid electrolyte film 47 and the negative electrode film48 were patterned to have an area of 49 mm² (7 mm (length)×7 mm(width)).

On the negative electrode film 48, a negative electrode currentcollector film 49 comprising metallic copper was formed by the vacuumdeposition method (FIG. 4D(13)). Herein, using a metallic mask (made ofSUS304) patterned to be in a prescribed from, the negative electrodecurrent collector film 49 was made to have a thickness of 1 μm and anarea of 49 mm² (7 mm (length)×7 mm (width)). A capacity of the batteryobtained here was 300 μAh.

Onto the silicon substrate 31 where the solid state battery was formed,a liquid epoxy resin (CEL-C-1102, manufactured by Hitachi Chemical Co.,Ltd.) was applied so as to be 1 μm thick, using a spin coater at arotation number of 1500 rpm. Subsequently, the applied liquid epoxyresin was heat cured at 150° C. for 3 hours to form a surface protectivelayer 50. Finally, using the above-described photolithography techniqueand the RIE dry etching device, the surface protective layer 50 waspatterned as shown in FIG. 4D(14) to obtain a battery mounted integratedcircuit device. The obtained battery mounted integrated circuit devicewas referred to as Device 1.

EXAMPLE 2

The battery mounted integrated circuit device as shown in FIG. 2 wasproduced in the same manner as in Example 1, except that the firstdiffusion layer and the wiring layer were formed so as to surround thesolid state battery mounted region. The battery mounted integratedcircuit device as thus obtained was referred to as Device 2.

[Evaluation]

In Devices 1 and 2 described above, the solid state battery wascharged/discharged in such a state that a positive potential (5V) notless than the potential of the positive electrode with respect to thenegative electrode was being applied, using an external power source, tothe first diffusion layer and the second diffusion layer. Here examinedwas the presence or absence of abnormalities in the basiccharacteristics of adjacent P-type and N-type MOS transistors.

As the basic characteristics, the Vd-Id characteristic and theon-voltage characteristic were investigated.

[V_(d)−I_(d) Characteristic]

First, voltages of 0 V to 5 V were successively applied to a drain ofthe N-type MOS transistor, with a voltage of 0 V, 1 V, 2 V, 3 V, 4 V or5 V applied to the gate, to measure a flowing drain current.

[On-Voltage]

With a voltage of 5 V applied to the drain, a voltage to be applied tothe gate (gate voltage) was increased and the gate voltage to make thedrain current 1 μA was measured.

In any of the measurements, the measured value was the same as thedesign value of the 5 V-level N-type MOS transistor.

A P-type MOS transistor was also examined on V_(d)−I_(d) characteristicand the on-voltage characteristic, in the same manner as above.

A voltage of 0 V to −5 V was successively applied to a drain, with avoltage of 0 V, −1 V, −2 V, −3 V, −4 V, or −5V applied to the gate, tomeasure a flowing drain current.

Also, with a voltage of −5 V applied to the drain, a voltage to beapplied to the gate (gate voltage) was increased in the minus direction,and the gate voltage to make the drain current −1 μA was measured.

In any of the measurements, the measured value was the same as thedesign value of the 5 V-level P-type MOS transistor.

As thus described, no abnormality was observed in the basiccharacteristic of the MOS transistors.

Furthermore, a battery mounted integrated circuit device was produced inthe same manner as in Example 1, except that the ratio of theconcentration of the N-type impurity in the first diffusion layer to theconcentration of the N-type impurity in the second diffusion layer was1×10¹, 1×10², 1×10³ or 1×10⁵. The obtained devices were referred to asDevice 3, Device 4, Device 5 and Device 6, respectively. It is to benoted that the concentration of the N-type impurity in the firstdiffusion layer was 1×10¹⁹/cm³.

In the same manner as above, the V_(d)−I_(d) characteristic and theon-voltage characteristic were measured in Devices 3 to 6.

As a result, in any device, abnormality in the basic characteristic ofthe MOS transistors was not observed.

As thus described, the battery mounted integrated circuit device of thepresent invention is capable of effectively preventing an integratedcircuit, formed on the same substrate as a solid state battery, frombeing contaminated by ions serving to charge/discharge the solid statebattery.

In the above described was a device where an integrated circuitcomprising semiconductor devices and a solid state battery are formed ona semiconductor substrate. The present invention can be applied not onlyto the case of mounting an integrated circuit comprising semiconductordevices, but to the case of mounting an integrated circuit comprisingelectronic devices.

Moreover, the present invention can be applied not only to the case ofusing the semiconductor substrate, but to the case of using anysubstrate where lithium ions diffuse. Furthermore, the present inventioncan be applied not only to a lithium-ion battery, but to a solid statebattery where alkaline metal ions serve to charge/discharge the battery.

INDUSTRIAL APPLICABILITY

According to the present invention, a battery mounted integrated circuitdevice can be provided which can effectively prevent deterioration incharacteristic of a semiconductor device and improper operation of thesemiconductor device, caused by diffusion of ions serving tocharge/discharge the solid state battery in the semiconductor substrate.

1. A battery mounted integrated circuit device, comprising: (1) asemiconductor substrate; (2) a solid state battery mounted on saidsemiconductor substrate; (3) an integrated circuit mounted on saidsemiconductor substrate; (4) a first diffusion layer, containing anN-type impurity, formed between a region of said semiconductor substratewhere said solid state battery is mounted and an region of saidsemiconductor substrate where said integrated circuit is mounted; and(5) a second diffusion layer, containing an N-type impurity, formedbelow said region of said semiconductor substrate where said solid statebattery is mounted, and overlapping with said first diffusion layer,said solid state battery comprising a positive electrode, a negativeelectrode, and a solid electrolyte disposed between said positiveelectrode and said negative electrode, the concentration of said N-typeimpurity in said first diffusion layer is higher than the concentrationof said N-type impurity in said second diffusion layer.
 2. The batterymounted integrated circuit device in accordance with claim 1, whereinthe concentration of said N-type impurity in said first diffusion layeris not less than 1×10¹⁹ atoms/cm³.
 3. The battery mounted integratedcircuit device in accordance with claim 1, wherein the ratio of theconcentration of said N-type impurity in said first diffusion layer tothe concentration of said N-type impurity in said second diffusion layeris not more than 1×10⁵.
 4. The battery mounted integrated circuit devicein accordance with claim 1, wherein said first diffusion layer and saidsecond diffusion layer have a positive potential.
 5. The battery mountedintegrated circuit device in accordance with claim 4, wherein saidpositive potential is not less than a potential of said positiveelectrode with respect to said negative electrode.
 6. The batterymounted integrated circuit device in accordance with claim 1, whereinsaid first diffusion layer surrounds said region where said solid statebattery is mounted.
 7. The battery mounted integrated circuit device inaccordance with claim 1, further comprising a wiring layer forconnecting said first diffusion layer with the outside.
 8. The batterymounted integrated circuit device in accordance with claim 1, furthercomprising a potential controlling section for controlling a potentialto be applied to said first diffusion layer and said second diffusionlayer.